Some integrated circuits need to operate on power-supply voltages that are quite low, as little as 1-3 volts. If such an integrated circuit contains an amplifier that amplifies a differential input signal, the low power-supply voltage severely constrains the voltage range of the common-mode voltage of the input signal. For this reason, a differential amplifier is often designed to have rail-to-rail input capability. That is, the amplified output signal is representative of the differential input voltage as its common-mode portion travels the full extent of the power-supply range.
A threshold voltage must be reached before a transistor becomes conductive. If the input stage of a differential amplifier utilizes only a single pair of input transistors in amplifying the input signal, achieving rail-to-rail input capability is very difficult. There is normally a high or low portion of the power-supply range where both transistors are turned off because their threshold voltages have not been reached. This problem can be circumvented by using complementary pairs of input transistors arranged in such a way that at least one of the pairs provides amplification when the common-mode input voltage is at any point in the power-supply range.
The transconductance of the input stage of a differential amplifier is an important measure of the overall performance capability of the amplifier. The input-stage transconductance, represented here by the symbol "G.sub.M ", is basically the rate of incremental change in total output current of the input stage to the incremental change in the differential portion of the input voltage.
Unless special precautions are taken, G.sub.M for an input stage that utilizes complementary pairs of input transistors is significantly greater when both pairs of transistors are conductive than when only one of the pairs is conductive. This variation in G.sub.M makes it difficult to optimize the frequency compensation for the amplifier when it is used in (or as) an operational amplifier with negative feedback. Significant distortion occurs at those values input common-mode voltage where each pair of input transistors switches between on and off. As a result, it is highly desirable that G.sub.M be largely constant as the common-mode voltage traverses the power-supply range.
U.S. Pat. No. 4,555,673 describes several embodiments of a differential amplifier which uses a current-steering technique to control G.sub.M for an input stage that employs complementary pairs of input transistors to attain rail-to-rail input capability. In all but one of the embodiments, the input transistors are bipolar devices. The transconductance for a bipolar transistor varies directly with its collector current. Accordingly, the transconductance for a pair of emitter-coupled like-polarity bipolar transistors is proportional to the tail (or operating) current provided jointly to the interconnected emitters of the transistors. For the bipolar embodiments, U.S. Pat. No. 4,555,673 takes advantage of this phenomenon to steer supply current to, or away from, the input transistors in such a way that the sum of the tail currents for the two pairs of input transistors is largely constant as the common-mode input voltage moves across the full power-supply range. G.sub.M for the amplifier is then largely constant.
The input transistors in the remaining embodiment in U.S. Pat. No. 4,555,673 are source-coupled insulated-gate FETs. In contrast to a bipolar transistor whose transconductance is largely proportional to its collector current, the individual transconductance for an insulated-gate FET varies with the square root of its drain current when the FET is in strong inversion and saturation. Due to this difference, G.sub.M for the input stage in the FET embodiment cannot be maintained largely constant by simply steering current to, or away from, the sources of the FETs in such a manner that the sum of the tail currents for the two complementary pairs of FETs is largely constant.
The G.sub.M control difficulty can be better understood by examining FIG. 1 which illustrates the FET embodiment of U.S. Pat. No. 4,555,673. The input stage of this differential amplifier centers around an N-channel input portion 10 and a P-channel input portion 12 that together amplify the difference V.sub.I between individual input voltages V.sub.I+ and V.sub.I-. The common-mode portion V.sub.CM of differential input voltage V.sub.I equals (V.sub.I+ +V.sub.I-)/2.
The differential amplifier in FIG. 1 operates between a high supply voltage V.sub.HH and a low supply voltage V.sub.LL. The range for the power-supply voltage V.sub.PS --i.e., V.sub.HH -V.sub.LL --is divided into three sub-ranges: (a) a high end range that extends from V.sub.HH down to a lower value referred to here as V.sub.MH, (b) a low end range that extends from V.sub.LL up to a higher value termed V.sub.ML, and (c) an intermediate range that extends between V.sub.MH and V.sub.ML.
Differential portion 10 contains substantially identical N-channel insulated-gate main FETs Q1 and Q2 which provide signal amplification up to V.sub.HH. Individual inputs V.sub.I+ and V.sub.I- are supplied to the gate electrodes of FETs Q1 and Q2. Their sources are connected together at a node NN through which a tail current I.sub.N flows. Portion 10 amplifies input V.sub.I by dividing tail current I.sub.N into main currents I.sub.1 and 1.sub.2 taken from the Q1 and Q2 drains. The difference between currents I.sub.1 and I.sub.2 is representative of input V.sub.I when common-mode voltage V.sub.CM is in the intermediate and high voltage ranges.
Similarly, differential portion 12 contains substantially identical P-channel insulated-gate main FETs Q3 and Q4 which furnish signal amplification down to V.sub.LL. Inputs V.sub.I+ and V.sub.I- are supplied to the gate electrodes of FETs Q3 and Q4. Their sources are connected together at a node NP through which a tail current I.sub.P flows. Portion 12 performs the amplification by dividing tail current I.sub.P into main currents I.sub.3 and I.sub.4 taken from the Q3 and Q4 drains. The difference between currents I.sub.3 and I.sub.4 is representative of V.sub.I when V.sub.CM is in the intermediate and low voltage ranges.
The remainder of the input stage shown in FIG. 1 consists of a current source 14 which supplies a constant current I.sub.L, a current source 16 which supplies a constant current I.sub.H, and a current-steering mechanism 18 which regulates the amounts of supply currents I.sub.L and I.sub.H provided to differential portions 10 and 12. Current-steering mechanism 18 is formed with insulated-gate FETs QN and QP and current-reversing circuits 20 and 22, all connected as indicated in FIG. 1. The input stage also contains a summing circuit which suitably combines main currents I.sub.1 -I.sub.4 to produce one or more output currents. The summing circuit is not explicitly depicted in U.S. Pat. No. 4,555,673 and, accordingly, is not shown here.
FIG. 2 is a G.sub.M graph that is useful in understanding how the differential amplifier of FIG. 1 typically operates. For this purpose, the intermediate section of the V.sub.PS range needs to be subdivided into a high transition zone extending between V.sub.MH and a lower voltage V.sub.TH, a low transition zone extending between V.sub.ML and a higher voltage V.sub.TL, and a central portion extending between V.sub.TH and V.sub.TL. AS V.sub.CM traverses the low transition zone in the positive direction, FETs Q1 and Q2 switch from off to fully on. Likewise, FETs Q3 and Q4 switch from off to fully on when V.sub.CM traverses the high transition zone in the negative direction.
FETs Q1-Q4 are all fully conductive when V.sub.CM is in the central portion of the intermediate range. Current-steering circuit 18 is inactive. Tail current I.sub.N equals I.sub.L, while tail current I.sub.P equals I.sub.H. As indicated in FIG. 2, G.sub.M is constant at a nominal value G.sub.MN in the central portion of the intermediate range.
It is possible to select the characteristics of current-reversing circuits 20 and 22 in such a manner that G.sub.M is largely equal to G.sub.MN when V.sub.CM is in the low end range where transistors Q1 and Q2 are turned off and supply current I.sub.P is greater than I.sub.H. Likewise, G.sub.M can be largely fixed at G.sub.MN across the high end range where FETs Q3 and Q4 are turned off and current I.sub.N is greater than I.sub.L. FIG. 2 illustrates this example.
Unfortunately, G.sub.M for the high and low transition zones climbs to a value significantly greater than G.sub.MN due to the square-root dependence of the individual transconductance of each of FETs Q1-Q4 on its drain current. In particular, G.sub.M in the transition zones typically reaches a maximum 15% above G.sub.MN. The increased G.sub.M in the transition zones is decidedly unattractive in some operational-amplifier applications.
There is a significant need for differential amplifiers that have FET inputs. Accordingly, it would be highly advantageous to have an FET-input differential amplifier that achieves both rail-to-rail input capability and substantially constant G.sub.M as V.sub.CM traverses the entire V.sub.PS range.